The present invention relates to a data input circuit provided in a data processing equipment and more particularly to such an input circuit having a latch circuit latching input data in asynchronism with a read request signal generated by a central processing unit (called hereinafter "CPU").
A data input circuit is interposed between one or more input terminals and a CPU. It receives the input data at the input terminals, latches the input data and, when CPU generates a read request signal, transfers the latched input data to the CPU in response thereto. Since the CPU generates the read request signal in accordance with programs to be executed, the read request signal is in asynchronism with the input data latching timing. For this reason, there occurs a case where the input circuit latches new input data while the CPU generates the read request signal. In this case, data to be supplied to the CPU is changed during the data read operation of the CPU. An error operation thereby occurs.